Quick Start

This guide walks you through applying TMR to a design using TMRX.

Procedure

  1. Create a configuration file tmrx_config.toml:

    [global]
tmr_mode = "LogicTMR"
insert_voter_after_ff = true
clock_port_names = ["clk_i", "clk"]
reset_port_names = ["rst_ni", "rst_n"]

  2. Create a Yosys synthesis script synth.ys:

    # Read design
read_verilog my_design.v
hierarchy -check -top top

# Standard synthesis
proc; opt
techmap

# Mark cells for TMR (run after optimization, before technology mapping)
tmrx_mark

# Technology mapping
read_liberty -lib cells.lib
dfflibmap -liberty cells.lib
abc -liberty cells.lib

# Apply TMR
tmrx -c tmrx_config.toml

# Final optimization
opt -noff
techmap
dfflibmap -liberty cells.lib
abc -liberty cells.lib

# Output
write_verilog -noattr output.v

  3. Run Yosys with the TMRX plugin:

    yosys -m build/tmrx.so -s synth.ys

Next Steps