Configuration Reference

TMR Mode Options

Option Type Default Description

tmr_mode

String

"LogicTMR"

The TMR strategy to apply
Valid Values
"None"

No TMR applied to this module.

"LogicTMR"

Triplicate internal logic with voters after FFs.

"FullModuleTMR"

Create wrapper with three module instances.

Voter Options

Option Type Default Description

tmr_voter

String

"Default"

Voter implementation to use

The "Default" voter implements a simple majority function using AND/OR gates:

  • Output: y = (a & b) | (a & c) | (b & c) (majority function)

  • Error: err = (a ^ b) | (b ^ c) (any mismatch detected)

Logic TMR Options

Configure in a [<scope>.logic] block such as [global.logic] or [module.alu.logic].

Option Type Default Description

insert_voter_after_ff

Bool

true

Insert voters after flip-flop outputs

insert_voter_before_ff

Bool

false

Insert voters before flip-flop inputs (planned, not yet implemented)

ff_cells

List

[]

Explicitly treat these cells as flip-flops

additional_ff_cells

List

[]

Add cells without replacing inherited ff_cells

excluded_ff_cells

List

[]

Remove cells from flip-flop treatment

logic_path_1_suffix

String

"_a"

Suffix for first redundant path

logic_path_2_suffix

String

"_b"

Suffix for second redundant path

logic_path_3_suffix

String

"_c"

Suffix for third redundant path

Full Module TMR Options

Configure in a [<scope>.full_module] block such as [global.full_module] or [group.critical.full_module].

Option Type Default Description

insert_voter_before_modules

Bool

false

Insert voters at module inputs

insert_voter_after_modules

Bool

true

Insert voters at module outputs

insert_voter_on_clock_nets

Bool

false

Allow voters on expanded clock nets

insert_voter_on_reset_nets

Bool

false

Allow voters on expanded reset nets

Port Preservation

Option Type Default Description

preserve_module_ports

Bool

false

Keep original module interface unchanged

prevent_renaming

Bool

false

Prevent FullModuleTMR worker-branch uniquification of this module
When preserve_module_ports = true

  • The module interface remains identical to the original.

  • Input signals are fanned out to all three redundant paths.

  • Output signals pass through voters to produce a single output.

  • Useful for drop-in replacement compatibility.

When preserve_module_ports = false

  • Input and output ports are triplicated (with suffixes like _a, _b, _c).

  • Clock and reset ports may be shared or triplicated based on expand_clock/expand_reset.

  • Parent modules must connect to all three port variants.

When prevent_renaming = true

  • A FullModuleTMR parent does not create branch-local renamed copies of this module.

  • The same module type is shared across the _a/_b/_c worker branches.

  • This only affects recursive branch uniquification.

  • It does not disable the internal _tmrx_impl clone or the internal wrapper/worker rename steps used by TMRX itself.

Clock and Reset Handling

Option Type Default Description

clock_port_names

List

["clk_i"]

Names of clock ports

reset_port_names

List

["rst_ni"]

Names of reset ports

expand_clock

Bool

false

Triplicate the clock network

expand_reset

Bool

false

Triplicate the reset network

Keep expand_clock = false and expand_reset = false unless you have specific requirements for clock/reset tree redundancy.

Clock and reset ports can also be identified using wire attributes (* tmrx_clk_port ) or ( tmrx_rst_port *) instead of name matching.

Flip-Flop Detection

Option Type Default Description

ff_cells

List

[]

Cell types to treat as flip-flops (extends auto-detection)

additional_ff_cells

List

[]

Add FF cells without overriding inherited ff_cells

excluded_ff_cells

List

[]

Cell types to exclude from FF treatment

TMRX automatically detects Yosys built-in FF types. Use these options to fine-tune detection:

[global.logic]
ff_cells = ["sg13g2_dfrbp_1"]

[module.special.logic]
additional_ff_cells = ["MY_CUSTOM_FF"]
excluded_ff_cells = ["sg13g2_dfrbp_1"]

Error Detection Options

Option Type Default Description

error_port_name

String

""

Name of the output port to use as the error sink (alternative to the tmrx_error_sink attribute)

auto_error_port

Bool

false

Automatically create a tmrx_err_o output port when no explicit error sink is present and voter errors exist

See Error Detection for full details on error sink methods and upward propagation.

Wire and Port Attributes

Attribute Description

tmrx_clk_port

Mark this wire as a clock signal

tmrx_rst_port

Mark this wire as a reset signal

tmrx_error_sink

Mark this output as the error aggregation point

tmrx_error_port_name

Module attribute: name of the port to use as the error sink (equivalent to error_port_name config option)

tmrx_auto_error_port

Module attribute: auto-create tmrx_err_o if no explicit error sink is present (equivalent to auto_error_port config option)

Reserved Groups

TMRX has built-in reserved groups that are automatically applied:

black_box_module

Applied when a module has the blackbox attribute, contains memories (has_memories), or contains processes (has_processes). Default behavior: tmr_mode = "FullModuleTMR".

cdc_module

Intended for Clock Domain Crossing modules. Default behavior: tmr_mode = "FullModuleTMR".

These groups are reserved. The automatic assignment behavior should not be relied upon to be overridden.